Altium

Design Rule Verification Report

Date: 2/17/2026
Time: 12:55:07 PM
Elapsed Time: 00:00:02
Filename: C:\Users\stein\Desktop\CubeSat\Control Board\PCB_Project\PCB.PcbDoc
Warnings: 0
Rule Violations: 4

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=0.152mm) (All),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=0.152mm) (Max=10.16mm) (Preferred=0.203mm) (All) 0
Routing Topology Rule(Topology=Shortest) (All) 0
Power Plane Connect Rule(Direct Connect )(Expansion=0.406mm) (Conductor Width=0.152mm) (Air Gap=0.152mm) (Entries=4) (All) 0
Minimum Annular Ring (Minimum=0.178mm) (All) 0
Hole Size Constraint (Min=0.33mm) (Max=6.731mm) (All) 0
Hole To Hole Clearance (Gap=0.254mm) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0mm) (All),(All) 0
Silk To Solder Mask (Clearance=0.152mm) (IsPad),(All) 0
Silk to Silk (Clearance=0mm) (All),(All) 0
Net Antennae (Tolerance=0mm) (All) 0
Board Clearance Constraint (Gap=0mm) (All) 4
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All) 0
Total 4

Board Clearance Constraint (Gap=0mm) (All)
Board Outline Clearance(Outline Edge): (0.375mm < 0.381mm) Between Board Edge And Pad J4-1(7mm,-61.625mm) on Multi-Layer
Board Outline Clearance(Outline Edge): (0.375mm < 0.381mm) Between Board Edge And Pad J4-2(11mm,-61.625mm) on Multi-Layer
Board Outline Clearance(Outline Edge): (0.325mm < 0.381mm) Between Board Edge And Pad J6-1(39.525mm,-61.675mm) on Multi-Layer
Board Outline Clearance(Outline Edge): (0.325mm < 0.381mm) Between Board Edge And Pad J6-2(43.525mm,-61.675mm) on Multi-Layer
Back to top